Samsung Electronics announces the launch of a production qualified as initial in 3 nm technology applying the Gate-All-Around (GAA) transistor architecture. The optimized 3nm process can reduce power consumption by 45%, improve performance by 23% and reduce chip area by 16% compared to 5nm technology.
Implemented for the first time, Samsung’s GAA technology dubbed MBCFET (Multi-Bridge-Channel FET) pushes back the performance limitations of FinFET technology, improving power efficiency by reducing the supply voltage level, while improving performance by increasing drive current capacity, says the Korean group. Samsung is launching the first application of its nanosheet transistor technology for the production of chips for high-performance, low-power computing applications and plans to expand it to mobile processors.
“We are looking to maintain our leadership with MBCFET which is the first 3nm process in the world. We will continue to actively innovate in the development of competitive technologies and build processes that will help accelerate technology maturity.”said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.
Samsung’s proprietary technology uses nanosheets with wider channels, which enable higher performance and greater power efficiency compared to GAA technologies using nanowires with narrower channels. By using 3nm GAA technology, Samsung claims to be able to adjust the channel width of the nanosheet to optimize power consumption and performance to meet various customer needs.
Compared with 5nm, the first-generation 3nm production process can reduce power consumption by up to 45%, improve performance by 23%, and reduce area by 16%, while the second-generation 3nm process will be able to reduce energy consumption by up to 50%, improve performance by 30% and reduce silicon area by 35%, says the Korean.
As technology nodes become smaller and chip performance requirements increase, IC designers are faced with the challenge of managing huge amounts of data to verify complex products with more functions. To meet these requirements, Samsung strives to provide a more stable design environment to reduce the time required for the design, verification and approval process, while improving product reliability. Since the third quarter of 2021, Samsung Electronics has provided an optimized design infrastructure with Samsung Advanced Foundry Ecosystem (SAFE) partners, including Ansys, Cadence, Siemens and Synopsys.